Dynamic random access memory (DRAM) chips are tested to verify the functionality of every memory cell within the DRAM chip. During the test, expected values are written to the memory cells of the DRAM chip and then the memory cells are read. If the data read from a memory cell matches the previously written data, the memory cell functionality is confirmed. If the data read from a memory cell does not match the previously written data, the memory cell fails. The failing memory cells are located and replaced with redundant memory cells.
One mode used to test DRAM chips is a compression test mode. The compression test mode is used to save test time and output pad connections for the test. During the compression test mode, the data read from the memory cells is not read at the output pads of the DRAM chip as in the normal read operation. Instead, the data that is read from the memory cells is compared to a read compression register and the result is compressed and passed to selected output pads. The bits on the selected output pads indicate which memory cells of the memory array are failing in the DRAM chip.
During the compression test mode, the data written to the memory array during the test is stored in a previously defined register. To write a certain pattern to the memory array, the design for test (DFT) design has to compensate for the topology of the memory array. Therefore, the register used to overwrite a memory cell has to be adapted depending on where the memory cell is located (e.g., to write solid physical ones to the memory array). The memory cell location is defined by the column address and row address associated with the memory cell.
On a DRAM chip, the topology of the memory array changes depending on the row as well as the column location. Therefore, the write and read compression register has to be changed according to the row address and column address of the memory cells being written. Typically, the write and read compression register is changed during the write and read bursts. A DRAM internal burst counter typically increments the column address during a read or write burst. During a write burst, the column address out of the internal burst counter is valid at each column access.
During a read burst on a DRAM, more than one column line is accessed in a sequential manner. Typically, the accessed columns are counted synchronously to the external clock through the burst counter. During the read burst, the data comes from the memory array and arrives at the data path after a delay. The data is then compared to the column address dependent write compression register. With an increase in the frequency requirement, the column address delivered by the internal burst counter is no longer valid at the time the data is valid at the data path. The column address may no longer be valid because the delay from the time the memory array is accessed to the time the data from the memory array is valid may be long enough to allow the burst counter to start counting the next column address associated with the next read burst.